发明名称 |
Synchronous to asynchronous to synchronous interface |
摘要 |
An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.
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申请公布号 |
US6848060(B2) |
申请公布日期 |
2005.01.25 |
申请号 |
US20010794467 |
申请日期 |
2001.02.27 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
COOK PETER W.;SCHUSTER STANLEY E. |
分类号 |
G06F13/42;G06F9/38;(IPC1-7):G06F13/42;G06F3/00 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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