发明名称 |
Data erasing method, and memory apparatus having data erasing circuit using such method |
摘要 |
The present invention is to propose an data erasing method, a memory apparatus, and a data erasing circuit which are able to reduce the time required to boost the potential of the semiconductor substrate thereby to reduce the time required to erase data. Namely, a memory apparatus having a data erasing circuit that erases stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate is disclosed. In this case, the data erasing circuit boosts a potential of the semiconductor substrate side while placing the control gate into its floating state; and applies an erasing voltage between the semiconductor substrate and the control gate to make the potential of the control gate to a predetermined potential.
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申请公布号 |
US2005012139(A1) |
申请公布日期 |
2005.01.20 |
申请号 |
US20040877980 |
申请日期 |
2004.06.29 |
申请人 |
SEKIMOTO SHUNJI;NAMISE TOMOHIRO |
发明人 |
SEKIMOTO SHUNJI;NAMISE TOMOHIRO |
分类号 |
G11C16/02;G11C16/04;G11C16/14;H01L21/8247;H01L27/10;H01L27/115;H01L29/423;H01L29/788;H01L29/792;(IPC1-7):H01L29/788 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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