发明名称 |
Wafer-level chip scale package and method for fabricating and using the same |
摘要 |
A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e.,interface) to the printed circuit board for any small die.
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申请公布号 |
US2005012225(A1) |
申请公布日期 |
2005.01.20 |
申请号 |
US20040852732 |
申请日期 |
2004.05.24 |
申请人 |
CHOI SEUNG-YONG;PARK MIN-HO;KIM JI-HWAN;JOSHI RAJEEV |
发明人 |
CHOI SEUNG-YONG;PARK MIN-HO;KIM JI-HWAN;JOSHI RAJEEV |
分类号 |
H01L21/60;H01L21/68;H01L23/31;H01L23/485;H01L23/525;(IPC1-7):H01L21/48;H01L23/52 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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