| 摘要 |
FIELD: microelectronics; integrated circuits using npn and pnp complementary bipolar transistors with carriers of different polarity of conductivity. ^ SUBSTANCE: proposed method provides for determining size of transistor emitter and base by degree of etching of silicon oxide thin layer to value as small as wished thereby enabling formation of complementary pair of transistors integrated in one transistor with emitter of one transistor being of ultra-submicron size and base of other transistor, of submicron size. Electrodes for base and emitter of transistor structure are formed on silicon oxide and actual area of electrodes-to-silicon contact that governs base and emitter size depends on amount of butt-end etching of silicon oxide to submicron or ultra-submicron size of as small value as desired. ^ EFFECT: enhanced speed of integrated circuits using proposed transistors. ^ 7 cl, 12 dwg |
