| 摘要 |
<P>PROBLEM TO BE SOLVED: To make a resolution by one clock of a master clock compatible with a phase synchronization range in a digital PLL circuit. <P>SOLUTION: In a numerical control oscillator. the master clock is variably divided, and a pattern for variably dividing the master clock by one period of a counter counting an output clock is weighted in accordance with an input numeric value so as to change it. Thus, the oscillator operates by the master clock. Consequently. the digital PLL circuit realizing resolution by one clock of the master clock and the wide phase synchronization range is constituted. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
