发明名称 |
APPARATUS AND METHOD FOR GENERATING ADDRESS FOR SRAM BUILT-IN SELF TEST CIRCUIT USING ONE UP-COUNTER |
摘要 |
PURPOSE: An apparatus and a method for generating an address for an SRAM(Static Random Access Memory) BIST(Built-In Self Test) circuit are provided to reduce size of the BIST circuit by using only one up-counter. CONSTITUTION: An apparatus for generating an address for a built-in self test circuit of a memory having addresses with the square of 2, and includes an up-counter(201), an inverter(203), and a selector(205). The up-counter(201) generates a first address(ADDR1) which is sequentially increased. The inverter(203) inverts the first address to generate a sequentially decreasing second address. The selector(205) selects either one of the first and second addresses in response to a control signal and outputs the selected result as the address to be tested.
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申请公布号 |
KR100468675(B1) |
申请公布日期 |
2005.01.20 |
申请号 |
KR19970035208 |
申请日期 |
1997.07.25 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JUN, HONG SIN;KIM, HEON CHEOL |
分类号 |
G01R31/28;G11C11/413;G11C29/12;G11C29/20;(IPC1-7):G01R31/26 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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