发明名称
摘要 A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.
申请公布号 JP2005502123(A) 申请公布日期 2005.01.20
申请号 JP20030525468 申请日期 2002.08.29
申请人 发明人
分类号 G06F9/30;G06F1/04;G06F1/08;G06F1/32;G06F9/38;G06F9/46;G06F9/48;G06F11/28;G06F11/36;G06F12/00;G06F12/02;G06F12/08;G06F13/28;G06F13/38;G06F13/42;H03L7/08;H03L7/095;H03L7/183;H04B1/40 主分类号 G06F9/30
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