发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a technology that can stably operate a PLL circuit. SOLUTION: A charge pump circuit 3 provided in a PLL circuit 100 is a constant current output type and charges and discharges the capacitor belonging to a loop filter with a constant current. Current that changes in accordance with the frequency controlled voltage VT outputted from the loop filter 4 is caused to flow to a voltage controlled oscillator (VCO) 5, and the rate of change of the current determines a voltage-frequency conversion gain Kv. When the electrical characteristics of a MOS transistor constituting the PLL circuit 100 fluctuate, the rates of change of constant current in the charge pump circuit 3 and of current in the VCO 5 fluctuate in an opposite direction. As a result of this, the conversion gain Kp of a phase comparing part 1 and the conversion gain Kv of the VCO 5 fluctuate in an opposite direction to be able to obtain the PLL circuit 100 whose total gain hardly fluctuates. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005020506(A) 申请公布日期 2005.01.20
申请号 JP20030184146 申请日期 2003.06.27
申请人 RENESAS TECHNOLOGY CORP;RENESAS DEVICE DESIGN:KK 发明人 TAZAKI YOSHIO;TAKEDA HIDENAO
分类号 H03L7/093;H03L7/099;(IPC1-7):H03L7/093 主分类号 H03L7/093
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