发明名称 |
System and method for instruction memory storage and processing based on backwards branch control information |
摘要 |
A system for instruction memory storage and processing in a computing device having a processor, the system is based on backwards branch control information and comprises a dynamic loop buffer (DLB) which is a tagless array of data organized as a direct-mapped structure; a DLB controller having a primary memory unit partitioned into a plurality of banks for controlling the state of the instruction memory system and accepting a program counter address as an input, the DLB controller outputs distinct signals. The system further comprises an address register located in the memory of the computing device, it is a staging register for the program counter address and an instruction fetch process that takes two cycles of the processor clock; and a bank select unit for serving as a program counter address decoder to accept the program counter address and to output a bank enable signal for selecting a bank in a primary memory unit, and a decoded address for access within the selected bank.
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申请公布号 |
US2005015537(A1) |
申请公布日期 |
2005.01.20 |
申请号 |
US20030620734 |
申请日期 |
2003.07.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ASAAD SAMEH W.;MORENO JAIME H.;RIVERS JUDE A.;WELLMAN JOHN-DAVID |
分类号 |
G06F9/38;G06F12/00;(IPC1-7):G06F12/00 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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