| 摘要 |
<p>In designing a scan test circuit, in the final stage element (101f) unit of a clock tree (T), a plurality of flip-flop circuits (102a to 102a, 102b to 102b, 102c to 102c, ...) driven by the final stage element (101f) are connected in series, thereby constituting a sub-scan chain. Moreover, sub-scan chains having a minimum relative stage difference (i.e., one stage difference) of the number of delay elements from the clock supply point (S) of the clock tree (T) are connected to one another. Furthermore, the sub-scan chains are connected to one another in such a manner that data is shifted from a flip-flop circuit having a large clock delay to a flip-flop circuit having a small clock delay. Accordingly, the number of delay elements inserted into the data line of the shift register as the hold time guarantee in the shift operation of the scan shift register is reduced, thereby reducing the power consumption.</p> |
