| 摘要 |
PURPOSE: A clock synchronized delay circuit is provided to suppress a common mode noise and to accurately adjust duty cycles of a clock signal by driving a clock delay locked circuit by using a differential clock signal. CONSTITUTION: A differential clock buffer(400) delays a differential clock signal from outside by a first delay time, buffers the delayed result, and outputs the results as a first clock signal and a first complementary clock signal. A dummy delay unit(410) delays the first clock signal by a second delay time, and outputs the result as a second clock signal. A first clock delay unit(420) includes plural series-connected unit delay units, receives the second clock signal, and outputs third clock signals having delay times different from one another. A comparator(430) compares phases of the first and third clock signals, latches the third clock signal in phase with the first clock signal, and generates first and second control signals in response to the latched result. A second clock delay unit(440) delays the first clock signal corresponding to the third delay time to output a fifth clock signal. A complementary delay unit(450) delays the first complementary clock signal corresponding to the third delay time to output a fifth complementary clock signal. The clock synchronized delay circuit further includes a clock driver(460) and a complementary clock driver(470).
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