发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT, LIBRARY DEVELOPMENT METHOD THEREOF AND LAYOUT METHOD
摘要 PROBLEM TO BE SOLVED: To solve the problems wherein it is difficult from a man-hour point of view to develop various kinds of I/O cell lineup while the development cycle of an ultra-fine process is shortened year by year, and low integration density of a low breakdown voltage element in an intra-integrated circuit I/O region results in the increase in chip size of entire integrated circuit. SOLUTION: An I/O cell library is developed by a hard macro library consisting of only a high breakdown voltage element, and a low breakdown voltage element which has conventionally existed in an I/O cell is developed as a soft macro library describing functions. By doing this, the number of steps of developing an I/O cell library is reduced. The hard macro library and the soft macro library which have been developed are applicable to a conventional layout design flow, and thus the increase in the number of man-hour can be prevented. By preventing the existence of the low breakdown voltage element in the I/O region, a power source wiring for intra-I/O region low breakdown voltage can be eliminated. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005019652(A) 申请公布日期 2005.01.20
申请号 JP20030181751 申请日期 2003.06.25
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SEGAWA KEIMEI
分类号 H01L21/82;(IPC1-7):H01L21/82 主分类号 H01L21/82
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