| 摘要 |
PROBLEM TO BE SOLVED: To provide a simplified communication system which is reduced in circuit scale by decreasing the number of communication lines and is light in communication load. SOLUTION: While a clock line besides a data line is equipped so as not to deteriorate a high-speed property and a packet transmission form of a clock synchronization type is adopted in a control line from a main CPU 23 to a sub CPU 25, a clock line is eliminated and only data line is equipped though the high-speed property is sacrificed in a control line from the sub CPU 25 to the main CPU 23. The main CPU 23 transmits packet data, in which the first byte is an index number, the second byte is a data value and the third byte is a check sum, to the sub CPU 25. On the other hand, the sub CPU 25 verifies the index number and the check sum and returns an acknowledge bit indicating the presence or absence of an communication error to the main CPU 23. COPYRIGHT: (C)2005,JPO&NCIPI
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