发明名称 INFORMATION PROCESSING SYSTEM AND MEMORY CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To realize a system capable of executing efficiently a plurality of threads in parallel, using a plurality of processors. SOLUTION: In this information processing system, each of the threads is able to execute a program only by accessing a local memory in the processor, without accessing a common memory, because the local memories LS0, LS1, LS2 are provided respectively in the plurality of processors LS0, LS1, LS2. The each thread performs efficient interaction with the mating thread, without being conscious of the processor from which the mating tread is dispatched, because the local memory, of the processor corresponding to the mating thread, mapped in an effective address EA space is changed automatically in response to the processor in which the mating thread for the interaction is executed. The plurality of threads are thereby executed efficiently in parallel. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005018620(A) 申请公布日期 2005.01.20
申请号 JP20030185416 申请日期 2003.06.27
申请人 TOSHIBA CORP 发明人 KANAI TATSUNORI;MAEDA SEIJI;YOSHII KENICHIRO
分类号 G06F12/08;G06F9/46;G06F9/50;G06F12/02;G06F12/06;G06F12/10;G06F15/16;G06F15/173;(IPC1-7):G06F9/46 主分类号 G06F12/08
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