| 摘要 |
PROBLEM TO BE SOLVED: To decrease a circuit scale without decreasing the number of gradations. SOLUTION: A D/A converting circuit has gate lines 8 and diffusion layers 9 which are arranged in a lattice shape and when an arbitrary MOS transistor Q1 arranged at an intersection of a gate line 8 and a diffusion layer 9 turns on, diffusion layers 9 on the right and left sides of the position of the above MOS transistor Q1 conduct through the MOS transistor Q1. When the D/A converting circuit 5 is laid out, four kinds of voltage candidate selection parts 11a to 11d selected with low-order two bits of a digital signal are arranged in a Y direction and a final voltage selection part 12 selected with high-order two bits of the digital signal is arranged in an X direction, thereby the number of diffusion layers 9 can greatly be decreased to decrease the number of MOS transistors Q1 arranged at the intersections of the diffusion layers 9 and gate lines 8, and the number of the diffusion layers can greatly be decreased to make the formation area of the D/A converting circuit 5 small. COPYRIGHT: (C)2005,JPO&NCIPI
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