发明名称 TRANSPARENT LATCH CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a transparent latch circuit capable of scan testing with a GSD. SOLUTION: In the transparent latch circuit 10, the test signal TE is low level at the regular operation. The latch stop circuit 5 outputsϕG5 of H level, therefore, the slave latch circuit 3 passes through the received signalϕM, a master latch circuit 2 works as a latch circuit corresponding to a signalϕIV4 output from the inverter 4. At the scan test time, the scan test signal TE becomes H level. At this time, the latch stop circuit 5 outputs theϕG5 as the complementary signal of the signalϕIV4. The master latch circuit 2 and the slave latch circuit 3 work as the latch circuits mutually responding to the complementary signals, and whole of the transparent latch circuit 10 works as a flip flop circuit. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005017207(A) 申请公布日期 2005.01.20
申请号 JP20030185054 申请日期 2003.06.27
申请人 INTERNATL BUSINESS MACH CORP 发明人 UEDA MAKOTO
分类号 G01R31/28;G01R31/3185;H03K3/037;(IPC1-7):G01R31/28 主分类号 G01R31/28
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