发明名称 |
Method of fabricating a field effect transistor structure with abrupt source/drain junctions |
摘要 |
Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.
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申请公布号 |
US2005012146(A1) |
申请公布日期 |
2005.01.20 |
申请号 |
US20040917722 |
申请日期 |
2004.08.12 |
申请人 |
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发明人 |
MURTHY ANAND S.;CHAU ROBERT S.;MORROW PATRICK;JAN CHIA-HONG;PACKAN PAUL |
分类号 |
H01L29/78;H01L21/20;H01L21/336;H01L29/08;H01L29/10;H01L29/16;H01L29/161;H01L29/417;(IPC1-7):H01L29/76 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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