发明名称 SYSTEM AND METHOD FOR PLACEMENT OF DUMMY METAL FILLS WHILE PRESERVING DEVICE MATCHING AND/OR LIMITING CAPACITANCE INCREASE
摘要 Systems and methods for limiting capacitance increase due to dummy fill metals utilized to improve planar profile uniformity are disclosed. A computer-automated method for locating dummy fills in an integrated circuit fabrication process generally comprises reading a layout file specifying layout of the integrated circuit, designating at least one net of the integrated circuit as a critical net, the critical nets being only a subset of all nets of the integrated circuit, identifying metal conductors corresponding to each designated critical net from the layout file, delineating a net blocking exclusion zone extending a distance of a minimum net blocking distance (NBD) from the metal conductor for each metal conductor identified, and locating the dummy fills outside of the net blocking exclusion zone.
申请公布号 KR20050007440(A) 申请公布日期 2005.01.18
申请号 KR20047014312 申请日期 2003.03.12
申请人 发明人
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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