发明名称 Multichip module
摘要 A selector has the first input terminal to which a test signal is given, the second input terminal connected to an output terminal of the first internal logic circuit, and an output terminal connected via a wiring to an input terminal of the second internal logic circuit. Another selector has an input terminal connected to the wiring, another input terminal connected to an output terminal of the second internal logic circuit, and an output terminal connected via another wiring to a signal input terminal of the second internal logic circuit. Each of the selectors selectively outputs a signal given to its first input terminal or a signal given to its second input terminal B based on a test mode signal.
申请公布号 US6844624(B1) 申请公布日期 2005.01.18
申请号 US20030732521 申请日期 2003.12.11
申请人 RENESAS TECHNOLOGY CORP. 发明人 KIRITANI MASAHIDE
分类号 H01L25/04;G01R31/28;G01R31/3185;H01L21/822;H01L27/04;(IPC1-7):H01L23/34 主分类号 H01L25/04
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