DELAY LOCKED LOOP WITH COARSE LOCK-FINE LOCK SCHEME USING TWO FEEDBACK SIGNALS HAVING PHASE DIFFERENCE

摘要

PURPOSE: A delay locked loop with coarse lock-fine lock scheme is provided to prevent the malfunction due to the jitter or the noise by using two feedback signals having a phase difference. CONSTITUTION: A delay locked loop with coarse lock - fine lock scheme used in a semiconductor memory device comprises a phase detector for generating a detecting signal corresponding to a phase difference between a feedback signal(PD input1 or PD input2) and an external clock signal(Ext clk) after comparing the external clock signal(Ext clk) with the feedback signal(PD input1 or PD input2); a delay control part for generating one of the first delay control signal or the second delay control signal after receiving the detecting signal; a coarse synchronizing part for generating a delay signal which is the first phase delayed signal of the external clock signal(Ext clk) according to the first delay control signal; a fine synchronizing part for generating a delay signal which is the second phase delayed signal of the external clock signal(Ext clk) according to the second delay control signal. Wherein, the phase detector compares the external clock signal(Ext clk) with each feedback signal(PD input1 or PD input2) and then determines whether generating the first delay control signal or generating the second delay control signal.