发明名称 Method for testing a circuit which is under test, and circuit configuration for carrying out the method
摘要 A circuit configuration for testing a circuit that is under test using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve actual data that are output by the circuit under test on the basis of supplied test data are compared with prescribed nominal data in the test device. A combinational logic device for logically combining the sequentially output test results is provided such that result data indicate fault free operation of the circuit under test only if the actual data which are output match the prescribed nominal data in all of the sequentially performed test procedures. The result data is output via an addressing and control unit in the circuit under test.
申请公布号 US2005010844(A1) 申请公布日期 2005.01.13
申请号 US20040889923 申请日期 2004.07.12
申请人 INFINEON TECHNOLOGIES AG 发明人 THALMANN ERWIN
分类号 G01R31/319;G11C29/48;(IPC1-7):G01R31/28;G06F11/00 主分类号 G01R31/319
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