发明名称 Low power chip architecture
摘要 An architecture for selectively powering a receive module (108) is disclosed. The architecture comprises the receive module (108) which is functionally adapted, while power is applied to the receive module (108) by a power module (601), and after a power-up time interval has elapsed, to process a traffic packet. The architecture further comprises the power module (601) that is adapted to apply power to the receive module 108 dependent upon arrival of a wake-up packet.
申请公布号 US2005007972(A1) 申请公布日期 2005.01.13
申请号 US20040879111 申请日期 2004.06.30
申请人 CANON KABUSHIKI KAISHA 发明人 PARAMESWARAN SRIDEVAN;PEDDERSEN JORGEN;PARTIS ASHLEY
分类号 H04L12/12;H04L12/26;(IPC1-7):H04L12/26 主分类号 H04L12/12
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