| 摘要 |
PROBLEM TO BE SOLVED: To realize reduction of layout area of a word line driving circuit in a ferroelectric memory device. SOLUTION: The ferroelectric memory device is provided with a memory cell MC000 having a ferroelectric capacitor, a word line control circuit WD00 of power supply voltage drive, a voltage level conversion circuit LS00 which converts the voltage level into a boosted voltage from the power supply voltage and a cell plate line driving circuit CPD00. A first signal at a power supply voltage level is outputted from the word line control circuit, the first signal is inputted into the voltage level conversion circuit, a second signal at the boosted voltage level is outputted from the voltage level conversion circuit, the second signal is a word line signal WL00 of a memory cell and the cell plate line driving circuit is constituted of a logic circuit of a cell plate driving signal CPS0 and the second signal. COPYRIGHT: (C)2005,JPO&NCIPI
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