发明名称 |
Processor device and method for data protection by means of data block scrambling |
摘要 |
A processor device and method for data protection by means of data block scrambling is disclosed, which has a processor core, a cache and a block scrambling/de-scrambling device. The processor core executes instructions of the processor and access data in a memory. The cache is connected to the processor core in order to provide it with a memory space for quickly accessing data. The block scrambling/de-scrambling device is coupled between the cache and the memory in order to scramble data block outputted by the cache based on a seed generated by a seed generator or to de-scramble data block inputted by the memory based on the seed.
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申请公布号 |
US2005008151(A1) |
申请公布日期 |
2005.01.13 |
申请号 |
US20040878323 |
申请日期 |
2004.06.29 |
申请人 |
SAMPLUS TECHNOLOGY CO., LTD. |
发明人 |
LIANG BOR-SUNG |
分类号 |
G06F12/08;G06F21/00;H04N7/167;(IPC1-7):H04N7/167 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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