发明名称 |
High level synthesis device, method for generating a model for verifying hardware, method for verifying hardware, control program, and readable recording medium |
摘要 |
A high level synthesis device includes a high level synthesis section for performing high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components; and a cycle accurate model generation section for generating a cycle accurate model, capable of verifying a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.
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申请公布号 |
US2005010387(A1) |
申请公布日期 |
2005.01.13 |
申请号 |
US20040850153 |
申请日期 |
2004.05.21 |
申请人 |
MORISHITA TAKAHIRO;OHNISHI MITSUHISA |
发明人 |
MORISHITA TAKAHIRO;OHNISHI MITSUHISA |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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