Semiconductor storage device

摘要

An operation control circuit is provided for shortening a transition time from a deep stand-by mode to a stand-by mode in a pseudo-SRAM having the deep stand-by mode and the stand-by mode. The transition from the deep stand-by mode to the stand-by mode starts first and second timer circuits 12 and 14 which respectively output a timer output TN of a constant cycle needed for self-refresh and a timing signal TR of a shorter cycle than a self-refresh cycle. A counter circuit 15 counts the output TR from the second timer circuit 14 immediately after the deep stand-by mode has been transitioned to the stand-by mode. If the counted value corresponds to a value as set, then the counter circuit 15 outputs an operation mode switching signal C. A selector circuit 17 comprising a multiplexer is switched and controlled by the output from the counter circuit 15. The selector circuit 17 remains selecting TR until the counted value of the counter circuit 15 corresponds to the set value, and in the subsequent stand-by mode, the selector circuit 17 selects and outputs TN.