| 摘要 |
A DLL clock control circuit determines whether or not an operating frequency is a low frequency satisfying a prescribed condition, based on signals received from a DLL circuit and a READ control circuit. When the DLL clock control circuit determines that the operating frequency is a low frequency, the DLL clock control circuit outputs a DLL clock received from the DLL circuit if a first signal to be activated in response to a READ command is activated, while when determining that an operating frequency is not a low frequency, outputting a DLL clock received from the DLL circuit if a second signal to be activated in response to an ACT command is activated. As a result, a semiconductor memory device can guarantees a data output operating in data reading and can reduce power consumption during active standby.
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