发明名称 |
Low-jitter clock distribution circuit |
摘要 |
A low-jitter clock distribution circuit, used in an integrated circuit having multiple analog-to-digital converters (ADCs), includes a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor. The ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter is equal to substantially the square root of the ratio Un/Up of the majority carrier mobilities of the N-channel and P-channel transistors as determined by the semiconductor fabrication process.
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申请公布号 |
US6842136(B1) |
申请公布日期 |
2005.01.11 |
申请号 |
US20030724296 |
申请日期 |
2003.11.28 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
AGARWAL NITIN;RATH SHAKTI SHANKAR |
分类号 |
G06F1/10;H03M1/08;H03M1/12;(IPC1-7):H03M1/12 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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