| 摘要 |
PURPOSE: A method of manufacturing an STI(Shallow Trench Isolation) layer of a semiconductor memory device is provided to remove seam from a first planarized insulating layer and to improve the flatness of a second planarized insulating layer by using annealing. CONSTITUTION: A plurality of trenches are formed in a semiconductor substrate(2). A first planarized insulating layer(14) for filling the trenches is deposited on the resultant structure by using an HARP(High Aspect Ratio Process). A second planarized insulating layer(16) is deposited on the first planarized insulating layer. Annealing is performed on the resultant structure to remove seam from the first planarized insulating layer. The first planarized insulating layer is an USG(Undoped Silicate Glass) layer. The second planarized insulating layer is made of one selected from a group consisting of a BPSG layer, a PSG layer or SOG layer.
|
