| 摘要 |
PURPOSE: A method for manufacturing a high integrated MOSFET device is provided to prevent loss of a gate spacer oxide layer and to improve symmetrical property by using a triple gate spacer of NON(Nitirde-Oxide-Nitride) structure. CONSTITUTION: A gate oxide layer(5), a conductive layer(6), a mask nitride layer(8) are sequentially formed on a silicon substrate(1) having an NMOS region(3) and a PMOS region(4). A gate pattern is formed by etching. A screen oxide layer(9) is formed at sidewalls of the exposed gate pattern and on the exposed substrate by re-oxidation processing. An LDD region(10) is formed in the substrate. A gate buffer oxide layer(11), a gate spacer nitride layer, a gate spacer oxide layer(13) and a barrier nitride layer(16) are sequentially formed on the resultant structure. After selectively exposing the PMOS region, spacer etching and ion-implantation processing for forming a P+ source/drain are sequentially performed. After selectively exposing the NMOS region, spacer etching and ion-implantation processing for forming an N+ source/drain are carried out.
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