发明名称 TECHNIQUE FOR REDUCING ESD LOAD CAPACITANCE
摘要 PROBLEM TO BE SOLVED: To enable to make electrostatic discharge (ESD) capacitance small, while maintaining a required ESD protection level, in ESD of high frequency application. SOLUTION: A capacitive load effect of an ESD circuit having an electrostatic protection diode is reduced by using a capacitance compensation circuit. In a normal operation in which static discharge does not occur, a capacitance reduction circuit maintains reverse bias in the electrostatic protection diode so that the capacitance of the diode is lower than a predetermined value. When static discharge occurs, the capacitance compensation circuit removes an applied reverse bias and the static discharge is made to be shunted to a power rail by the electrostatic protective diode. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005005705(A) 申请公布日期 2005.01.06
申请号 JP20040167178 申请日期 2004.06.04
申请人 SEIKO EPSON CORP 发明人 HARGROVE MICHAEL;PETROSKY JOSEPH
分类号 H01L27/04;H01L21/822;H01L21/8238;H01L27/02;H01L27/06;H01L27/092;H02H9/00;(IPC1-7):H01L21/822;H01L21/823 主分类号 H01L27/04
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