DELAY LOCKED LOOP AND METHOD FOR LOCKING CLOCK DELAY IN THE DELAY LOCKED LOOP BY USING DELAY LINE CONSISTING OF UNIT DELAY CELLS IN SERIES THAT HAVE DIFFERENT RESOLUTIONS

摘要

PURPOSE: A delay locked loop and a method for locking clock delay are provided to fix a phase promptly without an increase in layout size and to cope with a change of dynamic frequency. CONSTITUTION: A delay locked loop used in synchronous memory device comprises a phase comparison part for comparing a feedback clock having the same delay path of the real clock path with a buffered reference clock of the outer clock; a delay control part for outputting a control signal for shifting an inner clock in response to the comparison signal output from the phase comparison part; a delay line part for shifting the inner clock in response to the control signal from the delay control part. Wherein the delay line part consists of unit delay cells in series that have different resolutions.