发明名称 |
MULTIBIT MEMORY WITH DYNAMIC REFERENCE VOLTAGE GENERATION |
摘要 |
<p>A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).</p> |
申请公布号 |
WO2005001843(A1) |
申请公布日期 |
2005.01.06 |
申请号 |
WO2004US16015 |
申请日期 |
2004.05.21 |
申请人 |
SPANSION LLC;SHIEH, MING-HUEI;KURIHARA, KAZUHIRO |
发明人 |
SHIEH, MING-HUEI;KURIHARA, KAZUHIRO |
分类号 |
G11C11/56;G11C16/04;G11C16/28;(IPC1-7):G11C11/56 |
主分类号 |
G11C11/56 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|