发明名称 Multi-node computer system employing multiple memory response states
摘要 A system may include a node and an additional node coupled by an inter-node network. The node may include an active device, an interface to the inter-node network, a memory, and an address network coupling the active device, the interface, and the memory. The active device may send an address packet to initiate a transaction to gain an access right to a coherency unit. In response to receiving the address packet, the memory is configured to send data corresponding to the coherency unit to the active device dependent on memory response information associated with the coherency unit. If the transaction cannot be satisfied within the node, the memory is configured to forward a report corresponding to the address packet to the interface. In response to the report, the interface is configured to send the additional node a coherency message requesting the access right via the inter-node network.
申请公布号 US2005005075(A1) 申请公布日期 2005.01.06
申请号 US20040821370 申请日期 2004.04.09
申请人 SUN MICROSYSTEMS, INC. 发明人 LANDIN ANDERS;CYPHER ROBERT E.;WOOD DAVID A.;HAGERSTEN ERIK E.;HILL MARK D.
分类号 G06F12/00;G06F12/08;(IPC1-7):G06F12/00 主分类号 G06F12/00
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