| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an error detection circuit for detecting that there is an error at a comparatively high rate even when there is an error of three bits or more. <P>SOLUTION: An ECC code generating circuit 4 generates an ECC code on the basis of read data or write data from a data storage region 3a. A counter circuit 5 derives a count number with respect to the read data or the write data. An ECC code comparison circuit 6 compares the ECC code with respect to the read data with the ECC code with respect to the write data. A count number comparison circuit 7 compares the count number with respect to the read data with the count number with respect to the write data. An error detection correction circuit 8 detects an error of three bits or more of the read data on the basis of a comparison result from the ECC code comparison circuit 6 or a comparison result from the count number comparison circuit 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
