发明名称 DATA TRANSMISSION DEVICE AND INPUT/OUTPUT INTERFACE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a data transmission device and an input/output interface circuit with a jitter transmission circuit, capable of testing for jitter tolerance in data transmission/reception at the time of a mass production test and of improving a fault detection rate. SOLUTION: A clock generation circuit 5 supplies a clock signal TX_CK to a data transmission circuit 2 and supplies a clock signal RX_CK to a data reception circuit 3, for the purpose of a jitter proof test of a data transmission/reception circuit 1a. At that time, the clock signal TX_CK supplied to the data transmission circuit 2 by the clock generation circuit 5 is made to include the jitter that is depth of modulation and a modulation frequency according to each kind of setting signal. Because it is in time of the test, a signal TEST is in an H level. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005004653(A) 申请公布日期 2005.01.06
申请号 JP20030169872 申请日期 2003.06.13
申请人 FUJITSU LTD 发明人 YAMAGUCHI HISAKATSU
分类号 G06F1/04;G01R31/30;G01R31/317;H03K19/00;H03L7/06;H03L7/07;H04L1/20;H04L7/00;H04L25/00;H04L25/02;H04L25/40;(IPC1-7):G06F1/04 主分类号 G06F1/04
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