发明名称 APPARATUS FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent reset from occurring during burn-in tests on flip-flop circuits with a reset function/scan function constituting a scan chain. SOLUTION: An NOR circuit is constituted of pMOSs 30 and 31 and nMOSs 32 and 33, and an invertor circuit is constituted of pMOS 34 and nMOS 35. At scan shift operation, a signal of a signal level Hi is inputted to an operation mode switching signal input terminal SE of a selector 29 to select a scan test signal of SI. An internal reset signal XR is thereby fixed to the signal level Hi regardless of an input value of a reset signal from a reset signal input terminal RST. For normal operation, a signal of a signal level Low is inputted to the operation mode switching signal input terminal SE. It is thereby possible to perform normal reset control by the reset signal impressed on the reset signal input terminal RST. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005003392(A) 申请公布日期 2005.01.06
申请号 JP20030164104 申请日期 2003.06.09
申请人 SHARP CORP 发明人 NISHIMURA HOZUMI;SENDA HIROMASA
分类号 G01R31/28;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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