发明名称 Parallel adder-based DCT/IDCT design using cyclic convolution
摘要 The present invention provides a device and method for applying 1-D and 2-D DCT and IDCT transforms to sets of input data, typically 8x8 or 16x16 matrices of coefficients. In one embodiment, the present invention provides input lines, logic to pre-add input values and generate operands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform: The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the present invention may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic to pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.
申请公布号 US2005004963(A1) 申请公布日期 2005.01.06
申请号 US20040897486 申请日期 2004.07.23
申请人 发明人 GUO JIUN-IN;LIU KUN-WANG
分类号 G06F17/14;(IPC1-7):G06F17/14 主分类号 G06F17/14
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