| 摘要 |
An expanding module for serial transmission between a chip and a plurality of interface units is disclosed. The module is comprised of a plurality of first OR gates and a plurality of second OR gates, corresponding respectively to each interface unit, which logically evaluates the control signals and the data signals transmitted by the chip to the interface units, and an AND gate that logically judges the feedback data signals from the interface units to decide which interface unit is to communicate with the chip.
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