| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory circuit and a semiconductor memory device capable of increasing software error resistance. <P>SOLUTION: Each of the two inverter circuits of a CMOS (complementary metal oxide semiconductor) type memory cell has: two PMOS (p-channel MOS) transistors P1, P3 (P2, P4) serially connected between a power source and a memory node D (/D); and two NMOS (n-channel MOS) transistors N3, N5 (N4, N6) serially connected between a ground and the memory node D (/D). The gates of the P1, P3, N3, and N5 (P2, P4, N4 and N6) are connected in common to the memory node D (/D), and each of two access circuits has two serially connected NMOS transistors N1, N7 (N2, N8). The gates of the N1, N7 (N2, N8) are connected to a common bit line BL (/BL), and the body area of each of the MOS transistors constituting the inverter circuit and the access circuit is insulated and separated from the other. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
