| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory device capable of executing ECC (Error Check and Correct) processing without generating any delays in the reading/writing of a memory. SOLUTION: In a memory syste, an ECC circuit is not inserted onto a data path for data writing/reading. The ECC processing is performed during the cycle of normal data reading/writing processing, in such timing that it does not conflict with the data reading/writing processing in order not to cause a substantial delay in the data wiring/reading processing. Specifically, the ECC processing is performed during the cycle of burst transfer in which a plurality of data are successively input to or output from a shift register. Since no access is made to the memory cell array during the burst transfer cycle, the ECC processing does not cause a delay in the reading/writing processing. COPYRIGHT: (C)2005,JPO&NCIPI
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