METHOD AND DEVICE FOR LAYING OUT SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To increase the area and power of a semiconductor integrated circuit by inserting delay adjustment elements for compensating the occurrence of clock skews caused by manufacturing variations. SOLUTION: When the delay timeτLof a data line 306 is relatively small, the input/output flip-flop pairs 304, 305 of the data line 306 are selected so that a clock delay timeτCfrom the flip-flop pairs 304, 305 to a clock confluence point 307 gets shorter. This allows a reduction in the number of delay adjustment elements 309 that should be inserted to avoid hold errors while taking manufacturing variations into consideration. The area of a chip and the power consumed by the chip can be reduced. COPYRIGHT: (C)2005,JPO&NCIPI