发明名称 |
Process of protecting an element of an integrated circuit against silicide formation |
摘要 |
<p>Protection of a semiconductor material against the formation of a metal silicide comprises the formation, on the material, of a layer of silicon-germanium alloy using the following stages: (a) deposition of the layer of silicon-germanium alloy (10) on the integrated circuit assembly; (b) removal of this layer in the zones needed for the formation of a silicide; (c) deposition of a metal on the structure obtained by the removal; (d) formation of the metal silicide (110) on the defined zones; (e) removal of the metal which has not reacted and of the ternary metal-silicon-germanium alloy possibly formed; (f) removal of the layer of silicon-germanium alloy in order to expose the non silicide component.</p> |
申请公布号 |
EP1494270(A1) |
申请公布日期 |
2005.01.05 |
申请号 |
EP20040291490 |
申请日期 |
2004.06.14 |
申请人 |
STMICROELECTRONICS S.A. |
发明人 |
FROMENT, BENOIT;WACQUANT, FRANCOIS |
分类号 |
H01L21/285;(IPC1-7):H01L21/285 |
主分类号 |
H01L21/285 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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