Define overlay dummy pattern in mark shielding region to reduce wafer scale error caused by metal deposition

摘要

A new method is provided for the creation of a dummy pattern. A typical wafer exposure mask contains a Clear Out Window (CLWD) pattern, this CLWD pattern is of no value during the process of shielding the area on the surface of the wafer where the alignment mark must be placed. This CLWD can therefore be used to create a dummy overlay pattern, resulting in a reduction in the wafer scaling error that typically occurs as a result of metal deposition. For the same reasons, a dummy overlay pattern can also be created in the scribe lines of the wafer surface.