发明名称 Data transfer controller and electronic device
摘要 The objective is to provide a data transfer control device and electronic equipment that are capable of reducing processing overheads, thus enabling high-speed data transfer within a compact hardware configuration. In a data transfer control device in accordance with IEEE 1394, a packet shaping circuit (160) shapes each packet that is transferred in from another node into a form that can be used by an upper layer, and a packet division circuit (180) writes the header of the thus-shaped packet into a header area in RAM and the data thereof into a data area. A data pointer that has been passed from the packet division circuit is appended to the header of the packet during packet shaping. Tags are used to divide packets. Information indicating broadcast information, error status information, and whether or not the packet was received during a self-ID period is appended to the trailer of the packet during the packet shaping. The information, such as ACK, that was appended to the rearmost end of the packet in a time series during packet shaping is written to the start of the header of the packet in RAM. <IMAGE>
申请公布号 US6839347(B1) 申请公布日期 2005.01.04
申请号 US20000582294 申请日期 2000.06.23
申请人 SEIKO EPSON CORP 发明人 ISHIDA TAKUYA;KAMIHARA YOSHIYUKI;WADA FUMITOSHI
分类号 H04L12/40;H04L12/56;H04L12/64;H04L29/06;(IPC1-7):H04L12/28;H04J3/24 主分类号 H04L12/40
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