| 摘要 |
In a signal processing apparatus having a plurality of signal processing circuits where predetermined data is to be output sequentially through the plurality of signal processing circuits, when signal processing is performed at each signal processing circuit, timing necessary for respective signal processing is added to the data to be transmitted, as a header information, so that a complicated construction, such that a circuit for obtaining timing necessary for signal processing is added at each signal processing circuit, can be avoided, and the data can be securely processed and delivered at each signal processing circuit.
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