发明名称 |
Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits |
摘要 |
A mixed-voltage I/O buffer circuit that prevents leakages through a driver stage PMOS transistor is provided. The buffer circuit has a first part that prevents leakage through a parasitic diode of the transistor and a second part that prevents leakage through the transistor when the transistor is turned on by a signal on a bonding pad having a voltage level higher than a power supply voltage of the buffer circuit. The buffer circuit provides biases approximately equal to the high voltage signal to a gate and a substrate terminal of the PMOS transistor when the bonding pad has the high voltage signal thereon, and provides a bias approximately equal to the power supply voltage of the buffer circuit to the gate and substrate of the PMOS transistor when the bonding pad has a low voltage signal thereon.
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申请公布号 |
US6838908(B2) |
申请公布日期 |
2005.01.04 |
申请号 |
US20030400873 |
申请日期 |
2003.03.28 |
申请人 |
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE |
发明人 |
KER MING-DOU;CHUANG CHE-HAO;LEE KUO-CHUNG;JIANG HSIN-CHIN |
分类号 |
H03K19/003;(IPC1-7):H03K19/017;H03K19/094 |
主分类号 |
H03K19/003 |
代理机构 |
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主权项 |
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地址 |
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