发明名称
摘要 PURPOSE: A method for forming a bit line of a semiconductor device is provided to reduce a contact resistance and a delay time by forming an etch stop layer for a bit line. CONSTITUTION: An interlayer dielectric is formed on the entire surface of a semiconductor substrate including a landing plug poly. A bit line contact hole for exposing the landing plug poly is formed by etching the interlayer dielectric. An etch-stop layer is formed on the entire surface of the semiconductor substrate including the bit line contact hole by using Ti. A Ti layer having the thickness of 70 to 90 angstrom is formed under the pressure of 4 to 5 mTorr. An RTA(Rapid Thermal Anneal) process is performed under the temperature of 860 to 870 degrees centigrade. A bit line is connected to the landing plug poly through the bit line contact hole.
申请公布号 KR100464539(B1) 申请公布日期 2005.01.03
申请号 KR20030001701 申请日期 2003.01.10
申请人 发明人
分类号 H01L21/28 主分类号 H01L21/28
代理机构 代理人
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