发明名称 |
LADDERRTYPE CIRCUIT |
摘要 |
A ladder device comprising at least three ladder sections connected in cascade and weighting-factor adjusting means coupled to said ladder sections and which comprises first and second field effect transistors (FET) having channel regions with different predetermined length/width ratios that define a weighting factor coefficient. A further fine adjustment of the weighting factor is achieved by adjusting the gate voltages of the FETs. |
申请公布号 |
JPS53110444(A) |
申请公布日期 |
1978.09.27 |
申请号 |
JP19780025935 |
申请日期 |
1978.03.07 |
申请人 |
PHILIPS NV |
发明人 |
REONARUDO YAN MARIA ETSUSERU;RUDOFUIKASU GERARUDASU MARIA H |
分类号 |
G11C19/00;G11C19/28;G11C27/00;H01L21/339;H01L29/762;H01L29/78;H03H7/30;H03H11/26;H03H15/02 |
主分类号 |
G11C19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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