发明名称 |
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES HAVING PLANARIZED POLYCRYSTALLINE SILICON LAYER |
摘要 |
PURPOSE: A manufacturing method for semiconductor devices is provided to prevent a falling of a gate electrode by planarizing a curved portion of a polycrystalline silicon layer generated by a trench. CONSTITUTION: A trench is formed on a gate region on a surface of a substrate(21). A gate oxide layer(29) is formed on a front portion of the substrate having the trench. A polycrystalline silicon layer(31) having dopants therein is formed on a front portion of the substrate having the gate oxide layer. The polycrystalline silicon layer is planarized. A metallic silicide layer(33) and an upper insulating layer(35) for a gate are sequentially formed on the polycrystalline silicon layer. A photoresist pattern is formed on the upper insulating layer to form an isle-shape gate electrode(37) such that a surface of a source/drain region is exposed.
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申请公布号 |
KR20040110658(A) |
申请公布日期 |
2004.12.31 |
申请号 |
KR20030040071 |
申请日期 |
2003.06.20 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE, JIN WON |
分类号 |
H01L21/336;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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